| Summary of FPGA designs to date:
Xilinx was a very straight forward tool to design with. I was already familiar
with the Xilinx tools, as well as viewlogic schematic capture and simulation.
Altera's tool was fairly easy to use, but it had some differences from what I
was used to. One, Altera's schematic capture is entirely hierarchical, where
Viewlogic and Valid both use some sort of paging system. This created
confusion and slowed the design process. Secondly, Altera does not back
annotate simulation results to the schematic, which makes it difficult to
quickly debug a mistake. Next, the tool didn't warn me that I accidentally
shorted outputs to inputs with improper naming on some flops, and I had to
find it in simulation. Finally, I was surprised at the performance variation
possible by changing the routing constraints. In general, the design went
fairly well, but I would suggest using the tool you are comfortable with to
design with Altera, and not going with their schematic capture and simulation
to avoid the learning curve.
As for the Motorola, the actual design entry and simulation went fairly well.
Since it was viewlogic based, I had the same ease of use and comfort that I
had with Xilinx. One minor hiccup is that you must use the Viewlogic built-in
libraries In and Out signal on all i/o's, which is not clear in any of the
documentation. The place and route tools were very easy to use, and fairly
well documented with the on line help. My only real nit with the Motorola
tools is that their report files do not contain all the pertinent information
(Fmax, set up, tco) and that they do not have any static timing capability.
This is probably due to their immaturity in comparison to Xilinx and Altera,
and hopefully they will improve this shortly.
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