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| Title: | DIGITAL UNIX (FORMERLY KNOWN AS DEC OSF/1) |
| Notice: | Welcome to the Digital UNIX Conference |
| Moderator: | SMURF::DENHAM |
|
| Created: | Thu Mar 16 1995 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 10068 |
| Total number of notes: | 35879 |
8737.0. "U: need crash help !!!" by COLES1::LONZECK () Thu Feb 06 1997 12:07
Hello,
i hope any can help about the described problem.
I have a A0255 and the system crash three times/month with the following
DIA Messages.
I try to analyse the problem with the MCHK.exe V3.5 but i get only the
information that the Problem is the Module ? that used the Address,
described in epic_pear.
Is there a reference available for the register epic_pear to PCI/ISA
Slot ???
Problemdescription: (DIA V2.3)
dia -a -o full -R
DECevent V2.3
******************************** ENTRY 1 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 0.
Timestamp of occurrence 06-FEB-1997 15:11:20
Host name summer
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 300. Start-Up ASCII Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 3. Startup
ASCII Message
Alpha boot: available memory from 0x1016000 to 0x3ffe000
Digital UNIX V4.0B (Rev. 564); Thu Jan 16 13:58:38 MET 1997
physical memory = 64.00 megabytes.
available memory = 47.90 megabytes.
using 238 buffers containing 1.85 megabytes of memory
AlphaStation 255/233 system
DECchip 21071
82378IB (SIO) PCI/ISA Bridge
Firmware revision: 6.3
PALcode: OSF version 1.46
pci0 at nexus
psiop0 at pci0 slot 6
Loading SIOP: script 800800, reg 82008000, data 406ca7e0
scsi0 at psiop0 slot 0
rz0 at scsi0 target 0 lun 0 (LID=0) (DEC RZ26F (C) DEC 630J)
rz1 at scsi0 target 1 lun 0 (LID=1) (DEC RZ28M (C) DEC 0616)
rz4 at scsi0 target 4 lun 0 (LID=2) (DEC RRD45 (C) DEC 0436)
isa0 at pci0
gpc0 at isa0
ace0 at isa0
ace1 at isa0
lp0 at isa0
fdi0 at isa0
tga0 at pci0 slot 13
tga0: depth 8, map size 2MB, 1280x1024
tga0: ZLXp2-E, Revision: 34
tu0: DECchip 21040-AA: Revision: 2.4
tu0 at pci0 slot 14
tu0: DEC TULIP Ethernet Interface, hardware address: 00-00-F8-22-CB-0B
tu0: console mode: selecting 10BaseT (UTP) port: half duplex
lvm0: configured.
lvm1: configured.
kernel console: tga0
dli: configured
ATM Subsystem configured with 1 restart threads
ATM UNI 3.x signalling: configured
ATM IP interface: configured
******************************** ENTRY 2 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 3.
Timestamp of occurrence 06-FEB-1997 15:03:09
Host name summer
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 302. ASCII Panic Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 1. Panic
ASCII Message panic (cpu 0): Machine check - Hardware
error
******************************** ENTRY 3 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 2.
Timestamp of occurrence 06-FEB-1997 15:03:09
Host name summer
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
Byte Count x02E8
Processor Specific Offset x00000110
System Specific Offset x000001A0
PAL Error Type Code x00000201
PAL Frame Revision x00000001
- ALPHA CHIP REGISTERS -
PALTEMP1 x0000000000000009
PALTEMP2 x000C06F800000004
PALTEMP3 x0000000000000000
PALTEMP4 x0000000000000000
PALTEMP5 xFFFFFC0000E7A030
PALTEMP6 xFFFFFC00005065D0
PALTEMP7 x0000000000004200
PALTEMP8 x0000000000000400
PALTEMP9 x0000000000000007
PALTEMP10 xFFFFFC00004FE810
PALTEMP11 x0000000000000000
PALTEMP12 xFFFFFC00004FEBB0
PALTEMP13 xFFFFFC00004FEBE0
PALTEMP14 xFFFFFC00004FEC40
PALTEMP15 xFFFFFC00004FE9B0
PALTEMP16 xFFFFFC00004FE680
PALTEMP17 x0000000000000001
PALTEMP18 x000000011FFFFAC0
PALTEMP19 xFFFFFFFF8425FA38
PALTEMP20 xFFFFFC000069B2D0
PALTEMP21 x0000000000000000
PALTEMP22 x00505070727A7A7A
PALTEMP23 x0000000000000000
PALTEMP24 x0000000000000000
PALTEMP25 x0000000000010000
PALTEMP26 xFFFFFC0000E7A358
PALTEMP27 x0000000000000000
PALTEMP28 x00000000033D4000
PALTEMP29 xFFFFFFFC00000000
PALTEMP30 x0000000000000001
PALTEMP31 x0000000001297A38
Exception Address Reg xFFFFFC00005BC3FE
Exception Address Reg Provides Information
About The Most Recent Exception.
Address Points to Native-Mode Instruction
If Machine Check or Math Trap Exception,
PC in Exception Address is Correct.
Last Exception Addr PC: x3FFFFF000016F0FF
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
Icache Ctrl & Status Reg x000C06F800000004
Performance Counters Disabled
Empty Wrt Buffer Before Issuing Next Inst
Branch Prediction Selection: Not Taken
JSR Stack is Disabled
Instructions Can Only Single Issue
If Not in PALmode, Executing Reserved Inst
Opcode Will Result in OPCDEC Exception.
Super Page Istream Memory Mapping Disabled
Float Point Inst Will Cause FEN Exception
Icache Addr Space Numb: x0000000000000000
PALcode Base Address Reg x0000000000014000
PALcode Base Address: x0000000000000005
Hardware Int Enable Reg x0000000000000000
CRD Error Interrupts Disabled
Performance Cntr 0 & 1 Interrupts Disabled
Serial Line Interrupts Disabled
NO AST Interrupts Enabled In Any Mode
Hardware Int Request Reg x0000000000001040
NO Hrdw Int Req With Companion Enable Set
NO Softw Int Req With Companion Enable Set
NO AST Int Req With Companion Enable Set
CPU Hrdw Interrupt Request on Irq_h Pin 2
CPU Hrdw Interrupt Request on Irq_h Pin 4
Memory Management CSR x0000000000003640
MMCSR Valid Only on Mem Mgt Err, DTB Miss,
D-Stream Fault, Dcache Parity Error.
Last Faulting Instruction RA Field: R4
Last Faulting Instruction Opcode Follows:
x1B - Reserved for PALcode
(Data) Cache Status Reg x0000000000000003
This is EV45 Cache Status Register(C_STAT)
EV45 Chip is Production Version of 21064A
Last Load or Store Missed Dcache
Cache Address Reg x00000007FFFFFFFF
Abox Control Reg x000000000000942E
Machine Checks Enabled for Uncorr Errors
CRD Interrupts Enabled
Single Entry Icache Stream Buffer Enabled
Enable Super Page Dstream Virtual Addr Map
VA<33:13> to PA<33:13>, if VA<42:41>=2.
Lock Operation Conforms to Alpha Architect
Dcache Enabled
16K Byte Dcache Selected
Double Invalidate: Both EV45 Dcache Blocks
Addressed By iAdr_h<12:5> Invalidated.
Bus Interface Status Reg x0000000000000041
HARD ERROR Detected During External Cycle
BIU Command Cycle Type: Read_Block
Bus Interface Address Reg x0000000388100070
Address Only Valid if Bus Interface Status
Register Error Bit 0,1,2, or 3 is Set.
BIU Addr adr_h <4:2>: x4
BIU Addr adr_h<33:5>: x000000001C408003
Bus Interface Control Reg x0000000810002225
External Cache (Bcache) Enabled
PARITY MODE: External Cache Parity Enabled
Cache Rams are Output Enable Controlled
Ext Cache Rd Access Time: 3 CPU Cycles
Ext Cache Wrt Cycle Time: 3 CPU Cycles
Size of External Cache: 256 Kbyte
Ext Cache For Phys Addr Quad 3 Disabled
Ext Cache Rd Time Controlling Bcache Reads
Ext Cache Wrt En Ctrl: x0000000000000001
Fill Syndrome Reg x0000000000000000
No Error in Low Long Word of Quad Word
No Error in Upper Long Word of Quad Word
Fill Address Reg x0000000000019770
Addr Only Valid if Bus Interface Stat Reg
ECC(Bit 8) or PARITY(Bit 10) Error Set.
IF Bus Interface Stat Reg FILL_IRD Bit 11
is Clear, Cache Blk Phy Adr<4:2> is: x4
Cache Blk Phy Adr<33:5> x0000000000000CBB
Virtual Address Reg x0000000000006170
Dstream FLT/DTB Miss VA x0000000000006170
Bcache Tag Reg x0000000150000157
Last Bcache Access Resulted in a Hit
Parity Bit for Bcache Tag Status Bits Set
Bcache Tag Dirty Bit Set
Bcache Tag Shared Bit Clear
Bcache Tag Valid Bit Set
Bcache Tag Addrress Parity Bit Clear
Tag Being Probed: x000000000000000A
coma_gcr x00000000246300B4
DMA Priority
128 bit wide MEM
Bcache enabled
Bcache long writes
coma_edsr x00000000246321F0
coma_ter x0000000024633FF0
sysTag<21:17> = x0000000000001FF8
coma_elar x000000002463FFFF
sysBus<20:5> at time of e x000000000000FFFF
coma_ehar x0000000024631FFF
sysBus<33:21> at time of x0000000000001FFF
coma_ldlr x000000002463695A
sysBus<20:5> last locked x000000000000695A
coma_ldhr x0000000024630009
sysBus<31:21> last locked x0000000000000009
coma_base0 x0000000024630080
Reg Base Adr <33:23> = x0000000000000040
coma_base1 x0000000024630000
Reg Base Adr <33:23> = x0000000000000000
coma_base2 x0000000024630000
Reg Base Adr <33:23> = x0000000000000000
coma_cnfg0 x00000000246300EB
Bank Valid
Bank Size = 32 MB
Column Adr Selection x0000000000000003
coma_cnfg1 x000000002463004B
Bank Valid
Bank Size = 32 MB
Column Adr Selection x0000000000000001
coma_cnfg2 x0000000024630000
Bank Size = 1024 MB
Column Adr Selection x0000000000000000
epic_dcsr xFFFFFFFF801A003D
Translation buffer enabled
Prefetch enabled
Disable correctable error
Retry Timeout Error
Pass 2 Chip
Partial Bypass
PCI Cycle Type = Memory Read
epic_pear xFFFFFFFF88100070
PCI error address x0000000088100070
epic_sear x0000000000FDF540
DMA Address = x00000000000FDF54
epic_tbr1 x000000000080D000
Translation Base Adr = x0000000000004068
epic_tbr2 x0000000000000000
Translation Base Adr = x0000000000000000
epic_pbr1 x00000000008C0000
Scatter/Gather Enabled
Window Enabled
PCI Base Adr x0000000000000008
epic_pbr2 x0000000040080000
Scatter/Gather Disabled
Window Enabled
PCI Base Adr x0000000000000400
epic_pmr1 x0000000000700000
PCI Mask x0000000000000007
epic_pmr2 x000000003FF00000
PCI Mask x00000000000003FF
epic_harx1 xFFFFFFFF80000000
PCI_ad - memory space = x0000000000000010
epic_harx2 x0000000000000000
PCI_ad - memory space = x0000000000000000
epic_pmlt x00000000000000FF
Master Latency Timer = 255.
epic_tag0 x0000000000814000
pci_page x0000000000000102
epic_tag1 x0000000000800000
pci_page x0000000000000100
epic_tag2 x0000000000806000
pci_page x0000000000000101
epic_tag3 x0000000000802000
pci_page x0000000000000101
epic_tag4 x0000000000804000
pci_page x0000000000000100
epic_tag5 x0000000000806000
pci_page x0000000000000101
epic_tag6 x0000000000804000
pci_page x0000000000000100
epic_tag7 x0000000000812000
pci_page x0000000000000103
epic_data0 x0000000000001724
cpu_page x00000000000005C9
epic_data1 x00000000000006C2
cpu_page x00000000000001B0
epic_data2 x00000000000006C8
cpu_page x00000000000001B2
epic_data3 x00000000000006C4
cpu_page x00000000000001B1
epic_data4 x00000000000006C6
cpu_page x00000000000001B1
epic_data5 x00000000000006C8
cpu_page x00000000000001B2
epic_data6 x00000000000006C6
cpu_page x00000000000001B1
epic_data7 x0000000000001F00
cpu_page x00000000000007C0
******************************** ENTRY 4 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 1.
Timestamp of occurrence 06-FEB-1997 15:03:09
Host name summer
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 1. Severe Priority
Entry type 100. CPU Machine Check Errors
CPU Minor class 2. 660 Entry
Byte Count x02E8
Processor Specific Offset x00000110
System Specific Offset x000001A0
PAL Error Type Code x00000201
PAL Frame Revision x00000001
- ALPHA CHIP REGISTERS -
PALTEMP1 x000000200602A108
PALTEMP2 x000C06F800000004
PALTEMP3 xFFFFFFFFFFFFFFC6
PALTEMP4 x0000002000148870
PALTEMP5 xFFFFFFFFFFFFFFE3
PALTEMP6 x000000000000003B
PALTEMP7 x0000000000004200
PALTEMP8 x0000000000000400
PALTEMP9 x0000000000000000
PALTEMP10 xFFFFFC00004FE810
PALTEMP11 x0000000000000000
PALTEMP12 xFFFFFC00004FEBB0
PALTEMP13 xFFFFFC00004FEBE0
PALTEMP14 xFFFFFC00004FEC40
PALTEMP15 xFFFFFC00004FE9B0
PALTEMP16 xFFFFFC00004FE680
PALTEMP17 xFFFFFFFFFFFFFE46
PALTEMP18 x000000011FFFFAC0
PALTEMP19 xFFFFFFFF8425FA38
PALTEMP20 xFFFFFC000069B2D0
PALTEMP21 x0000000000000000
PALTEMP22 x00505070727A7A7A
PALTEMP23 x0000000000000000
PALTEMP24 x0000000000000000
PALTEMP25 x0000000000010000
PALTEMP26 x000000200602A128
PALTEMP27 x0000000000000000
PALTEMP28 x00000000033D4000
PALTEMP29 xFFFFFFFC00000000
PALTEMP30 x0000000000000001
PALTEMP31 x0000000001297A38
Exception Address Reg x0000000000014125
Exception Address Reg Provides Information
About The Most Recent Exception.
Address Points to PALmode Instruction
If Machine Check or Math Trap Exception,
On Return Subtract 4 from Exception PC.
Last Exception Addr PC: x0000000000005049
Exception Summary Reg x0000000000000000
Exception Mask Reg x0000000000000000
Icache Ctrl & Status Reg x000C06F800000004
Performance Counters Disabled
Empty Wrt Buffer Before Issuing Next Inst
Branch Prediction Selection: Not Taken
JSR Stack is Disabled
Instructions Can Only Single Issue
If Not in PALmode, Executing Reserved Inst
Opcode Will Result in OPCDEC Exception.
Super Page Istream Memory Mapping Disabled
Float Point Inst Will Cause FEN Exception
Icache Addr Space Numb: x0000000000000000
PALcode Base Address Reg x0000000000014000
PALcode Base Address: x0000000000000005
Hardware Int Enable Reg x00000000000014F0
CRD Error Interrupts Enabled
CPU Hrdw Interrupts Enabled Irq_h Pins 0,2
CPU Hrdw Interrupts Enbld Irq_h Pins 3,4,5
Performance Cntr 0 & 1 Interrupts Disabled
Serial Line Interrupts Disabled
NO AST Interrupts Enabled In Any Mode
Hardware Int Request Reg x0000000000001442
Any Hrdw Int Req With Companion Enable Set
NO Softw Int Req With Companion Enable Set
NO AST Int Req With Companion Enable Set
CPU Hrdw Interrupt Request on Irq_h Pin 0
CPU Hrdw Interrupt Request on Irq_h Pin 2
CPU Hrdw Interrupt Request on Irq_h Pin 4
Memory Management CSR x0000000000003F01
MMCSR Valid Only on Mem Mgt Err, DTB Miss,
D-Stream Fault, Dcache Parity Error.
D-Stream Reference Error Caused by Write
Last Faulting Instruction RA Field: R16
Last Faulting Instruction Opcode Follows:
x1F - Reserved for PALcode
(Data) Cache Status Reg x0000000000000003
This is EV45 Cache Status Register(C_STAT)
EV45 Chip is Production Version of 21064A
Last Load or Store Missed Dcache
Cache Address Reg x00000007FFFFFFFF
Abox Control Reg x000000000000942E
Machine Checks Enabled for Uncorr Errors
CRD Interrupts Enabled
Single Entry Icache Stream Buffer Enabled
Enable Super Page Dstream Virtual Addr Map
VA<33:13> to PA<33:13>, if VA<42:41>=2.
Lock Operation Conforms to Alpha Architect
Dcache Enabled
16K Byte Dcache Selected
Double Invalidate: Both EV45 Dcache Blocks
Addressed By iAdr_h<12:5> Invalidated.
Bus Interface Status Reg x0000000000000050
Bus Interface Address Reg x00000000000060E0
Address Only Valid if Bus Interface Status
Register Error Bit 0,1,2, or 3 is Set.
BIU Addr adr_h<33:5>: x0000000000000307
Bus Interface Control Reg x0000000810002225
External Cache (Bcache) Enabled
PARITY MODE: External Cache Parity Enabled
Cache Rams are Output Enable Controlled
Ext Cache Rd Access Time: 3 CPU Cycles
Ext Cache Wrt Cycle Time: 3 CPU Cycles
Size of External Cache: 256 Kbyte
Ext Cache For Phys Addr Quad 3 Disabled
Ext Cache Rd Time Controlling Bcache Reads
Ext Cache Wrt En Ctrl: x0000000000000001
Fill Syndrome Reg x0000000000000000
No Error in Low Long Word of Quad Word
No Error in Upper Long Word of Quad Word
Fill Address Reg x0000000000006100
Addr Only Valid if Bus Interface Stat Reg
ECC(Bit 8) or PARITY(Bit 10) Error Set.
Cache Blk Phy Adr<33:5> x0000000000000308
Virtual Address Reg x0000000000006170
Dstream FLT/DTB Miss VA x0000000000006170
Bcache Tag Reg x6624006624482848
Last Bcache Access Resulted in a Miss
Parity Bit for Bcache Tag Status Bits Clr
Bcache Tag Dirty Bit Clear
Bcache Tag Shared Bit Set
Bcache Tag Valid Bit Clear
Bcache Tag Addrress Parity Bit Asserted
Tag Being Probed: x0000000000004142
coma_gcr x000000007FB200B4
DMA Priority
128 bit wide MEM
Bcache enabled
Bcache long writes
coma_edsr x000000007FB221F0
coma_ter x000000006FB13FF0
sysTag<21:17> = x0000000000001FF8
coma_elar x000000006FB1FFFF
sysBus<20:5> at time of e x000000000000FFFF
coma_ehar x000000006FB11FFF
sysBus<33:21> at time of x0000000000001FFF
coma_ldlr x000000006FB1695A
sysBus<20:5> last locked x000000000000695A
coma_ldhr x000000006FB10009
sysBus<31:21> last locked x0000000000000009
coma_base0 x000000006FB10080
Reg Base Adr <33:23> = x0000000000000040
coma_base1 x000000006FB10000
Reg Base Adr <33:23> = x0000000000000000
coma_base2 x0000000047FF0000
Reg Base Adr <33:23> = x0000000000000000
coma_cnfg0 x0000000047FF00EB
Bank Valid
Bank Size = 32 MB
Column Adr Selection x0000000000000003
coma_cnfg1 x0000000047FF004B
Bank Valid
Bank Size = 32 MB
Column Adr Selection x0000000000000001
coma_cnfg2 x0000000047FF0000
Bank Size = 1024 MB
Column Adr Selection x0000000000000000
epic_dcsr xFFFFFFFF801E007D
Translation buffer enabled
Prefetch enabled
Disable correctable error
Retry Timeout Error
Lost Error
Pass 2 Chip
Partial Bypass
PCI Cycle Type = Memory Write
epic_pear xFFFFFFFF88629C08
PCI error address x0000000088629C08
epic_sear x0000000000FDF540
DMA Address = x00000000000FDF54
epic_tbr1 x000000000080D000
Translation Base Adr = x0000000000004068
epic_tbr2 x0000000000000000
Translation Base Adr = x0000000000000000
epic_pbr1 x00000000008C0000
Scatter/Gather Enabled
Window Enabled
PCI Base Adr x0000000000000008
epic_pbr2 x0000000040080000
Scatter/Gather Disabled
Window Enabled
PCI Base Adr x0000000000000400
epic_pmr1 x0000000000700000
PCI Mask x0000000000000007
epic_pmr2 x000000003FF00000
PCI Mask x00000000000003FF
epic_harx1 xFFFFFFFF80000000
PCI_ad - memory space = x0000000000000010
epic_harx2 x0000000000000000
PCI_ad - memory space = x0000000000000000
epic_pmlt x00000000000000FF
Master Latency Timer = 255.
epic_tag0 x0000000000814000
pci_page x0000000000000102
epic_tag1 x0000000000801000
Entry Valid
pci_page x0000000000000100
epic_tag2 x0000000000807000
Entry Valid
pci_page x0000000000000101
epic_tag3 x0000000000803000
Entry Valid
pci_page x0000000000000101
epic_tag4 x0000000000805000
Entry Valid
pci_page x0000000000000100
epic_tag5 x0000000000806000
pci_page x0000000000000101
epic_tag6 x0000000000804000
pci_page x0000000000000100
epic_tag7 x0000000000812000
pci_page x0000000000000103
epic_data0 x0000000000001724
cpu_page x00000000000005C9
epic_data1 x00000000000006C2
cpu_page x00000000000001B0
epic_data2 x00000000000006C8
cpu_page x00000000000001B2
epic_data3 x00000000000006C4
cpu_page x00000000000001B1
epic_data4 x00000000000006C6
cpu_page x00000000000001B1
epic_data5 x00000000000006C8
cpu_page x00000000000001B2
epic_data6 x00000000000006C6
cpu_page x00000000000001B1
epic_data7 x0000000000001F00
cpu_page x00000000000007C0
******************************** ENTRY 5 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 0.
Timestamp of occurrence 30-JAN-1997 13:32:57
Host name summer
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 300. Start-Up ASCII Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 3. Startup
ASCII Message
Alpha boot: available memory from 0x1016000 to 0x3ffe000
Digital UNIX V4.0B (Rev. 564); Thu Jan 16 13:58:38 MET 1997
physical memory = 64.00 megabytes.
available memory = 47.90 megabytes.
using 238 buffers containing 1.85 megabytes of memory
AlphaStation 255/233 system
DECchip 21071
82378IB (SIO) PCI/ISA Bridge
Firmware revision: 6.3
PALcode: OSF version 1.46
pci0 at nexus
psiop0 at pci0 slot 6
Loading SIOP: script 800800, reg 82008000, data 406ca7e0
scsi0 at psiop0 slot 0
rz0 at scsi0 target 0 lun 0 (LID=0) (DEC RZ26F (C) DEC 630J)
rz1 at scsi0 target 1 lun 0 (LID=1) (DEC RZ28M (C) DEC 0616)
rz4 at scsi0 target 4 lun 0 (LID=2) (DEC RRD45 (C) DEC 0436)
isa0 at pci0
gpc0 at isa0
ace0 at isa0
ace1 at isa0
lp0 at isa0
fdi0 at isa0
tga0 at pci0 slot 13
tga0: depth 8, map size 2MB, 1280x1024
tga0: ZLXp2-E, Revision: 34
tu0: DECchip 21040-AA: Revision: 2.4
tu0 at pci0 slot 14
tu0: DEC TULIP Ethernet Interface, hardware address: 00-00-F8-22-CB-0B
tu0: console mode: selecting 10BaseT (UTP) port: half duplex
lvm0: configured.
lvm1: configured.
kernel console: tga0
dli: configured
ATM Subsystem configured with 1 restart threads
ATM UNI 3.x signalling: configured
ATM IP interface: configured
******************************** ENTRY 6 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 1.
Timestamp of occurrence 30-JAN-1997 13:20:30
Host name summer
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 301. Shutdown ASCII Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 2. Shutdown
ASCII Message System rebooted by root
******************************** ENTRY 7 ********************************
Logging OS 2. Digital UNIX
System Architecture 2. Alpha
Event sequence number 0.
Timestamp of occurrence 29-JAN-1997 08:52:15
Host name summer
System type register x0000000D AlphaStation 400 or 2xx
Number of CPUs (mpnum) x00000001
CPU logging event (mperr) x00000000
Event validity 1. O/S claims event is valid
Event severity 5. Low Priority
Entry type 300. Start-Up ASCII Message Type
SWI Minor class 9. ASCII Message
SWI Minor sub class 3. Startup
ASCII Message
Alpha boot: available memory from 0x1016000 to 0x3ffe000
Digital UNIX V4.0B (Rev. 564); Thu Jan 16 13:58:38 MET 1997
physical memory = 64.00 megabytes.
available memory = 47.90 megabytes.
using 238 buffers containing 1.85 megabytes of memory
AlphaStation 255/233 system
DECchip 21071
82378IB (SIO) PCI/ISA Bridge
Firmware revision: 6.3
PALcode: OSF version 1.46
pci0 at nexus
psiop0 at pci0 slot 6
Loading SIOP: script 800800, reg 82008000, data 406ca7e0
scsi0 at psiop0 slot 0
rz0 at scsi0 target 0 lun 0 (LID=0) (DEC RZ26F (C) DEC 630J)
rz1 at scsi0 target 1 lun 0 (LID=1) (DEC RZ28M (C) DEC 0616)
rz4 at scsi0 t
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