| Title: | Alpha Workstation Conference |
| Notice: | See note 1.* for conference notices |
| Moderator: | WRKSYS::HOUSE |
| Created: | Wed Sep 07 1994 |
| Last Modified: | Fri Jun 06 1997 |
| Last Successful Update: | Fri Jun 06 1997 |
| Number of topics: | 1996 |
| Total number of notes: | 9122 |
Hi,
My customer is going to benchmark his application on the AS 500/500
tomorrow & he is asking me on the cache speed of the AS 500/500. Does
anyone know the speed of the following cache level ?
Could someone pls help ?
Thanxs in advance.
Cache size on chip 8 KB I
8 KB D
96KB level 2
Cache size on board 8 MB
Thanxs.
Rgds,
Poh Ing
| T.R | Title | User | Personal Name | Date | Lines |
|---|---|---|---|---|---|
| 1884.1 | More notes | WRKSYS::DISCHLER | I don't wanna wait in vain | Fri Mar 07 1997 08:30 | 4 |
See wrksys::alphastation500 note 84
or type DIR/TITLE=MEM DIR/TITLE=CACHE
RJD
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| 1884.2 | 82.1 in wrksys::alphastation500 | WRKSYS::DISCHLER | I don't wanna wait in vain | Fri Mar 07 1997 10:10 | 1 |
Also, note 82.1 is good - in wrksys::alphastation500 | |||||
| 1884.3 | Those notes don't cover the on-chip caches. | WIBBIN::NOYCE | Pulling weeds, pickin' stones | Fri Mar 07 1997 11:04 | 11 |
For the on-chip caches, the answer (in cycles) is the same for all EV5/EV56
systems:
8KB D - can read 2 64-bit values every cycle, or write 1 64-bit value.
read latency is 2 cycles (issue load, wait, use result).
(Thus for AS500/500, read bandwidth = 8 Gbytes/sec, latency = 4 nsec.)
96KB L2 - can read or write a 32-byte chunk every other cycle (so for
sequential access its bandwidth matches the D-cache). Read
latency from load to use is *about* 10 cycles. (Thus for AS500/500,
read bandwidth = 8 GB/sec, latency = ~ 20nsec.)
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