Conference ricks::dechips

Hi,

I'm in the process of "upgrading" a presentation about EV4 and EV5 to EV6, for 
our upcoming DECUS symposium.  Most of the information I need, I already found 
in the �P Forum presentation, and the �P Report.  But there are two numbers I am 
unable to find, although IMHO there's no reason to keep them secret.

Page size:		Is the page size still 8 kB?
Virtual address range:	43 bits?

Can someone confirm/deny/correct these numbers?

Thanks,

Roger

    
    Page size:	8Kb
    Virtual address range: 48 bits

    The 48b virtual address mode is enabled via a mode bit and 
    requires supporting page tables/tb fill flows.  Early users
    will likely stay with the 43b mode.
    
    Ed 

.7>     The 48b virtual address mode is enabled via a mode bit and 

Nice solution.

I have another question:
I don't really understand the slide notes on page 13 of A264UP1.PPT.

"
key fcn ofmapper is 80cams ... every cycle 8 virtual i comes out and do 8x80 
cams
virtual comes out of physicall ...
doing 640 cams per cycle ...
" etc.

It would definitely help if I would know what CAM stands for - but I sure 
wouldn't mind some help with the rest of the text/calculations on that page;-}

Thanks,

Roger

A CAM is a Contents Addressed Memory.
For a TLB you have a CAM and a RAM.
You present the CAM with some bits of the address.
If the mapping is present in the CAM, a hit line
fires.  That causes the right line of the RAM
to send you its contents.

The quote you have above hardly parses using an English grammar.
640 cams per cycle... doesn't make much sense.  Maybe something
else is meant.

R.

    I don't have the slides, but the comment is attempting to describe the 
    register mapping hardware.  In order to support 4 instructions per
    cycle you have up to 8 source and 4 destination registers.  To avoid 
    unnecessary pipeline stalls (due to WAR and WAW register dependancies), 
    we provide more physical registers than the 32 architecturally defined, 
    virtual registers.  This virtual to physical mapping requires that each 
    cycle we need to compare all incoming source register specifiers to the 
    complete register map state to determine which physical register holds 
    the source register data.  Since there are 80 physical registers, we 
    need to compare 8 source registers against 80 physical register
    mappings to determine the physical location of each source - so 8 X 80 
    compares take place each cycle.  The CAM, as described earlier, is a 
    comparitor which can also store state.  Since the virt-phy mapping 
    changes as you write new destination registers, you need to constantly 
    update the values being compared.  Doing this every 2ns is a real trick. 
    And it simultaneously occurs for fp registers (4 X 72). 
    
    Ed 
    

Now that's pretty neat...  Thanks for the explanation Ed.

Thanks!

Roger